1. Field of the Invention
The present invention relates to a data processing apparatus and, more particularly, to control of writing and reading operations of reproduction data to/from a memory.
2. Related Background Art
Hitherto, a digital video tape recorder (VTR) such that an image signal is digitized, compressed and encoded, and recorded or reproduced to/from a tape has been known.
In such a digital VTR, errors of the digital signal reproduced from the tape are corrected by using parity data added at the time of the recording and an expanding and decoding process which is opposite to the process upon recording is performed, thereby obtaining a reproduction image signal.
With respect to data whose errors cannot be corrected (error uncorrectable data), by performing what is called an interpolating process to replace such error uncorrectable data by correctly reproduced data before and after the erroneous data, a deterioration of a reproduction image is prevented. FIG. 1 is a block diagram showing a constructional example of such an interpolation circuit.
In FIG. 1, image data subjected to an error correcting process is inputted to a switch 201 and is stored into memories 203 and 204 each having a capacity of one frame through the switch 201. An error flag indicating that input data is the error uncorrectable data is inputted to a switch 202 and is alternately stored into flag memories 205 and 206 by every amount of one frame through the switch 202. Each of the flag memories 205 and 206 can store error flags of one frame.
In the digital VTR, a shuffling process is executed in which the image data, reproduced in accordance with the order of a raster scan, is read out on a frame unit basis in accordance with the order (different from the reproducing order) of a decoding process executed at the post stage. Since the order of the data which is written into each memory and the order of the data which is read out differ, one memory for each frame is necessary, namely, total two memories are needed.
The image data stored in the memories 203 and 204 is alternately read out through a switch 207 and is outputted to a delay circuit 210 and a circuit at the post stage through a switch 209.
A control circuit 211 controls (the switches 201 and 202) and (the switch 207 and a switch 208), thereby controlling writing and reading operations to/from the memories.
The error flags read out from the flag memories 205 and 206 are outputted to the switch 209 through the switch 208. When the read data is judged to be error data on the basis of the error flags, the switch 209 is connected to the delay circuit 210 side. In the other cases, the switch 209 is connected to the switch 207 side.
The delay circuit 210 delays output data of the switch 209 by a time of one frame and outputs the delayed data to the switch 209. By constructing as mentioned above, an interframe interpolation is accepted to interpolate the uncorrectable data by the data of a frame preceding to the frame of the uncorrectable data by one frame, so that a deterioration in picture quality of the reproduction image can be prevented.
In the conventional apparatus as mentioned above, however, the memory for interpolation of one frame is needed in addition to the data memory for shuffling the reproduction image data. Consequently, there is a problem in that the memory capacity of the whole circuit increases.